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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Serial Input PLL Frequency Synthesizer The MC12206 is a 2.0GHz Bipolar monolithic serial input phase locked loop (PLL) synthesizer with pulse-swallow function. It is designed to provide the high frequency local oscillator signal of an RF transceiver in handheld communication applications. Motorola's advanced Bipolar MOSAICTM V technology is utilized for low power operation at a minimum supply voltage of 2.7V. The device is designed for operation over 2.7 to 5.5V supply range for input frequencies up to 2.0GHz with a typical current drain of 7.4mA. The low power consumption makes the MC12206 ideal for handheld battery operated applications such as cellular or cordless telephones, wireless LAN or personal communication services. A dual modulus prescaler is integrated to provide either a 64/65 or 128/129 divide ratio. For additional applications information, two InterActiveApNoteTM documents containing software (based on a Microsoft Excel spreadsheet) and an Application Note are available. Please order DK305/D and DK306/D from the Motorola Literature Distribution Center. MC12206 MECL PLL COMPONENTS Serial Input PLL Frequency Synthesizer 16 * Low Power Supply Current of 6.7mA Typical for ICC and 0.7mA Typical for IP 1 * Supply Voltage of 2.7 to 5.5V * Dual Modulus Prescaler With Selectable Divide Ratios of 64/65 or 128/129 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 * On-Chip Reference Oscillator/Buffer * Programmable Reference Divider Consisting of a Binary 14-Bit Programmable Reference Counter 20 1 * Programmable Divider Consisting of a Binary 7-Bit Swallow Counter and an 11-Bit Programmable Counter * Phase/Frequency Detector With Phase Conversion Function * Balanced Charge Pump Outputs * Dual Internal Charge Pumps for Bypassing the First Stage of the Loop Filter to Decrease Lock Time DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E-03 * Outputs for External Charge Pump * Operating Temperature Range of -40C to +85C * Space Efficient Plastic Surface Mount SOIC or TSSOP Packages MAXIMUM RATINGS* Symbol VCC VP Tstg Parameter Power Supply Voltage, Pin 4 (Pin 5 in 20-lead package) Power Supply Voltage, Pin 3 (Pin 4 in 20-lead package) Storage Temperature Range Value -0.5 to +6.0 VCC to +6.0 -65 to +150 Unit VDC VDC C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. MOSAIC V, Mfax and InterActiveApNote are trademarks of Motorola, Inc. 1/97 (c) Motorola, Inc. 1997 1 REV 3 MC12206 R 16 P 15 fOUT BISW 14 13 FC 12 LE 11 DATA 10 CLK 9 Pinout: 16-Lead Package (Top View) 1 2 3 4 VCC 5 Do FC 15 6 GND LE 14 7 LD DATA 13 8 fIN NC 12 CLK 11 OSCin OSCout VP R 20 NC 19 P 18 fOUT BISW 17 16 Pinout: 20-Lead Package (Top View) 1 OSCin 2 3 4 VP 5 VCC 6 Do 7 GND 8 LD 9 NC 10 fIN NC OSCout PIN NAMES Pin OSCin OSCout VP VCC Do GND LD fIN CLK DATA LE I/O I O -- -- O -- O I I I I Function Oscillator input. A crystal is connected between OSCin and OSCout. An external source can be AC coupled into this input Oscillator output. Pin should be left open if external source is used Power supply for charge pumps (VP should be greater than or equal to VCC) VP provides power to the Do, BISW and P outputs Power supply voltage input. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. Internal charge pump output. Do remains on at all times Ground Lock detect, phase comparator output Prescaler input. The VCO signal is AC-coupled into this pin Clock input. Rising edge of the clock shifts data into the shift registers Binary serial data input Load enable input (with internal pull up resistor). When LE is HIGH or OPEN, data stored in the shift register is transferred into the appropriate latch (depending on the level of control bit). Also, when LE is HIGH or OPEN, the output of the second internal charge pump is connected to the BISW pin Phase control select (with internal pull up resistor). When FC is LOW, the characteristics of the phase comparator and charge pump are reversed. FC also selects fp or fr on the fOUT pin Analog switch output. When LE is HIGH or OPEN ("analog switch is ON") the output of the second charge pump is connected to the BISW pin. When LE is LOW, BISW is high impedance Phase comparator input signal. When FC is HIGH, fOUT=fr, programmable reference divider output; when FC is LOW, fOUT=fp, programmable divider output Output for external charge pump. Standard CMOS output level Output for external charge pump. Standard CMOS output level No connect 16-Lead Pkg Pin No. 1 2 3 4 5 6 7 8 9 10 11 20-Lead Pkg Pin No. 1 3 4 5 6 7 8 10 11 13 14 FC I 12 15 BISW O 13 16 fOUT P R NC O O O -- 14 15 16 -- 17 18 20 2, 9, 12, 19 MOTOROLA 2 HIPERCOMM BR1334 -- Rev 4 MC12206 15-BIT SHIFT REGISTER 15 15-BIT LATCH 14 1 PROGRAMMABLE REFERENCE DIVIDER OSCin OSCout CRYSTAL OSCILLATOR 14-BIT REFERENCE COUNTER fr PHASE/FREQUENCY DETECTOR CHARGE PUMP 1 LE LE DATA 7 CLK 7-BIT LATCH 7 CONTROL BIT DATA 18-BIT SHIFT REGISTER 11 DIVIDER OUTPUT MUX fOUT LD P R FC Do CHARGE PUMP 2 BISW 11-BIT LATCH 11 fIN PRESCALER 64/65 or 128/129 PROGRAMMABLE DIVIDER 7-BIT SWALLOW A-COUNTER 11-BIT PROGRAMMABLE N-COUNTER fp CONTROL LOGIC Figure 1. MC12206 Block Diagram HIPERCOMM BR1334 -- Rev 4 3 MOTOROLA MC12206 DATA ENTRY FORMAT The three wire interface of DATA pin, CLK (clock) pin and LE (load enable) pin controls the serial data input of the 14-bit programmable reference divider plus the prescaler setting bit, and the 18-bit programmable divider. A rising edge of the clock shifts one bit of serial data into the internal shift registers. Depending upon the level of the control bit, stored data is transferred into the latch when load enable pin is HIGH or OPEN. Control bit: "H" = data is transferred into 15-bit latch of programmable reference divider "L" = data is transferred into 18-bit latch of programmable divider WARNING: Switching CLK or DATA after the device is programmed may generate noise on the charge pump outputs which will affect the VCO. PROGRAMMABLE REFERENCE DIVIDER 16-bit serial data format for the programmable reference counter, "R-counter", and prescaler select bit (SW) is shown below. If the control bit is HIGH, data is transferred from the 15-bit shift register into the 15-bit latch which specifies the R divide ratio (8 to 16383) and the prescaler divide ratio (SW=0 for /128/129, SW=1 for /64/65). An R divide ratio less than 8 is prohibited. For Control bit (C) = HIGH: SETTING BIT FOR PRESCALER DIVIDE RATIO (FIRST BIT) MSB CONTROL BIT (LAST BIT) LSB S W R 14 R 13 R 12 R 11 R 10 R 9 R 8 R 7 R 6 R 5 R 4 R 3 R 2 R 1 C SETTING BITS FOR DIVIDE RATIO OF PROGRAMMABLE REFERENCE COUNTER (R-COUNTER) DIVIDE RATIO OF PROGRAMMABLE REFERENCE (R) COUNTER Divide Ratio R 8 9 * 16383 R 14 0 0 * 1 R 13 0 0 * 1 R 12 0 0 * 1 R 11 0 0 * 1 R 10 0 0 * 1 R 9 0 0 * 1 R 8 0 0 * 1 R 7 0 0 * 1 R 6 0 0 * 1 R 5 0 0 * 1 R 4 1 1 * 1 R 3 0 0 * 1 R 2 0 0 * 1 R 1 0 1 * 1 PRESCALER SELECT BIT Prescaler Divide Ratio P 128/129 64/65 SW 0 1 MOTOROLA 4 HIPERCOMM BR1334 -- Rev 4 MC12206 PROGRAMMABLE DIVIDER 19-bit serial data format for the programmable divider is shown below. If the control bit is LOW, data is transferred from the 18-bit shift register into the 18-bit latch which specifies the swallow A-counter divide ratio (0 to 127) and the programmable N-counter divide ratio (16 to 2047). An N-counter divide ratio less than 16 is prohibited. For Control bit (C) = LOW: MSB (FIRST BIT) CONTROL BIT (LAST BIT) LSB N 18 N 17 N 16 N 15 N 14 N 13 N 12 N 11 N 10 N 9 N 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 C SETTING BITS FOR DIVIDE RATIO OF PROGRAMMABLE N-COUNTER SETTING BITS FOR DIVIDE RATIO OF SWALLOW A-COUNTER DIVIDE RATIO OF PROGRAMMABLE N-COUNTER Divide Ratio N 16 17 * 2047 N 18 0 0 * 1 N 17 0 0 * 1 N 16 0 0 * 1 N 15 0 0 * 1 N 14 0 0 * 1 N 13 0 0 * 1 N 12 1 1 * 1 N 11 0 0 * 1 N 10 0 0 * 1 N 9 0 0 * 1 N 8 0 1 * 1 DIVIDE RATIO OF SWALLOW A-COUNTER Divide Ratio A 0 1 * 127 A 7 0 0 * 1 A 6 0 0 * 1 A 5 0 0 * 1 A 4 0 0 * 1 A 3 0 0 * 1 A 2 0 0 * 1 A 1 0 1 * 1 DIVIDE RATIO SETTING fvco = [(P*N)+A]*fosc / R with A N18:MSB (SW:MSB) N17 (R14) N8 (R7) A7 (R6) A1 (R1) C = CONTROL BIT (LAST BIT) (C = CONTROL BIT (LAST BIT)) CLK LE ts(CLE) ts(D) th(D) tCW tEW NOTES:Programmable reference divider data shown in parenthesis. Data shifted into register on rising edge of CLK. ts(D) = Setup Time DATA to CLK ts(D) 10ns th(D) = Hold Time DATA to CLK th(D) 20ns tCW = CLK Pulse Width tCW 30ns tEW = LE Pulse Width tEW 20ns ts(CLE) = Setup Time CLK to LE ts(CLE) 30ns Figure 2. Serial Data Input Timing HIPERCOMM BR1334 -- Rev 4 5 MOTOROLA MC12206 PHASE CHARACTERISTICS/VCO CHARACTERISTICS The phase comparator in the MC12206 is a high speed digital phase frequency detector circuit. The circuit determines the "lead" or "lag" phase relationship and time difference between the leading edges of the VCO (fp) signal and the reference (fr) input. Since these edges occur only once per cycle, the detector has a range of 2 radians. The phase comparator outputs are standard CMOS rail-to-rail levels (VP to GND for P and VCC to GND for R), designed for up to 20MHz operation into a 15pF load. These phase comparator outputs can be used along with an external charge pump to enhance the PLL characteristics. The operation of the phase comparator is shown in Figures 3 and 5. The phase characteristics of the phase comparator are controlled by the FC pin. The polarity of the phase comparator outputs, R and P, as well as the charge pump output Do can be reversed by switching the FC pin. H fr L H fp L H LD L Source Z Sink H L H P (FC = H) L Source Z Sink H L H P (FC = L) L NOTES: Do and BISW are current outputs. Phase difference detection range: -2 to +2 Spike difference depends on charge pump characteristics. Also, the spike is output in order to diminish dead band. When fr > fp or fr < fp, spike might not appear depending upon charge pump characteristics. Do (FC = H) BISW (LE = H or Open) R (FC = H) Do (FC = L) BISW (LE = H or Open) R (FC = L) Internal Charge Pump Gain [ Isource Isink 4p ) + 4mA 4p Figure 3. Phase/Frequency Detector, Internal Charge Pump and Lock Detect Waveforms MOTOROLA 6 HIPERCOMM BR1334 -- Rev 4 MC12206 For FC = HIGH: fr lags fp in phase OR fp>fr in frequency When the phase of fr lags that of fp or the frequency of fp is greater than fr, the P output will remain in a HIGH state while the R output will pulse from LOW to HIGH. The output pulse will reach a minimum 50% duty cycle under a 180 out of phase condition. The signal on R indicates to the VCO to decrease in frequency to bring the loop into lock. fr leads fp in phase OR fp fr = fp in phase and frequency When the phase and frequency of fr and fp are equal, the output P will remain in a HIGH state and R will remain in a LOW state except for voltage spikes when signals are in phase. This situation indicates that the loop is in lock and the phase comparator will maintain the loop in its locked state. When FC = LOW, the operation of the phase comparator is reversed from the above explanation. For FC = LOW: fr lags fp in phase OR fp>fr in frequency When the phase of fr lags that of fp or the frequency of fp is greater than fr, the R output will remain in a LOW state while the P output will pulse from HIGH to LOW. The output pulse will reach a minimum 50% duty cycle under a 180 out of phase condition. The signal on P indicates to the VCO to increase in frequency to bring the loop into lock. fr leads fp in phase OR fp fr = fp in phase and frequency When the phase and frequency of fr and fp are equal, the output P will remain in a HIGH state and R will remain in a LOW state except for voltage spikes when signals are in phase. This situation indicates that the loop is in lock and the phase comparator will maintain the loop in its locked state. The FC pin controls not only the phase characteristics, but also controls the fOUT test pin. The FC pin permits the user to monitor either of the phase comparator input signals, fr or fp, at the fOUT output providing a test mode where the programming of the dividers and the output of the counters can be checked. When FC is HIGH, fOUT = fr, the programmable reference divider output. When FC is LOW, fOUT = fp, the programmable divider output. Hence, If VCO characteristics are like (1), FC should be set HIGH or OPEN. fOUT = fr If VCO characteristics are like (2), FC should be set LOW. fOUT = fp VCO OUTPUT FREQUENCY (1) FC = HIGH or OPEN Do fp < fr fp > fr fp = fr H L Z R L H L P L H H fOUT fr fr fr Do L H Z FC = LOW R H L L P H L H fOUT fp fp fp (2) VCO INPUT VOLTAGE NOTES:Z = High impedance When LE is HIGH or Open, BISW has the same characteristics as Do. Figure 4. VCO Characteristics Figure 5. Phase Comparator, Internal Charge Pump, and fOUT Characteristics HIPERCOMM BR1334 -- Rev 4 7 MOTOROLA MC12206 fr 0 R 1 PHASE FREQUENCY DETECTOR V 1 UP P DOWN fp 0 R LD PHASE COMPARATOR CHARGE PUMP 1 FC CHARGE PUMP 2 LE BISW Do Figure 6. Detailed Phase Comparator Block Diagram LOCK DETECT The Lock Detect (LD) output pin provides a LOW pulse when fr and fp are not equal in phase or frequency. The output is normally HIGH. LD is designed to be the logical NORing of the phase frequency detector's outputs UP and DOWN. See Figure 6. In typical applications the output signal drives external circuitry which provides a steady LOW signal when the loop is locked. See Figure 9. OSCILLATOR INPUT For best operation, an external reference oscillator is recommended. The signal should be AC-coupled to the OSCin pin through a coupling capacitor. In this case, no connection to OSCout is required. The magnitude of the AC-coupled signal must be between 500 and 2200 mV peak-to-peak. To optimize the phase noise of the PLL when used in this mode, the input signal amplitude should be closer to the upper specification limit. This maximizes the slew rate of the signal as it switches against the internal voltage reference. The device incorporates an on-chip reference oscillator/buffer so that an external parallel-resonant fundamental crystal can be connected between OSCin and OSCout. External capacitor C1 and C2 as shown in Figure 10 are required to set the proper crystal load capacitance and oscillator frequency. The values of the capacitors are dependent on the crystal chosen (up to a maximum of 30 pF each including parasitic and stray capacitance). DUAL INTERNAL CHARGE PUMPS ("ANALOG SWITCH") Due to the pure Bipolar nature of the MC12206 design, the "analog switch" function is implemented with dual internal charge pumps. The loop filter time constant can be decreased by bypassing the first stage of the loop filter with the charge pump output BISW as shown in Figure 7 below. This enables the VCO to lock in a shorter amount of time. When LE is HIGH or OPEN ("analog switch is ON"), the output of the second internal charge pump is connected to the BISW pin, and the Do output is ON. The charge pump 2 output on BISW is essentially equal to the charge pump 1 output on Do. When LE is LOW, BISW is in a high impedance state and Do output is active. CHARGE PUMP 1 Do LPF-1 LPF-2 VCO CHARGE PUMP 2 LE BISW Figure 7. "Analog Switch" Block Diagram MOTOROLA 8 HIPERCOMM BR1334 -- Rev 4 MC12206 ELECTRICAL CHARACTERISTICS (VCC = 2.7 to 5.5V; TA = -40 to +85C) Symbol ICC Parameter Supply Current for VCC Min Typ 6.7 8.1 IP Supply Current for VP 0.7 0.8 FIN FOSC Operating Frequency Operating Frequency (OSCin) fINmax fINmin 2000 500 12 20 40 VIN VOSC VIH VIL IIH IIL IOSC IIH IIL ISource6 ISink6 IHi-Z VOH Output HIGH Voltage (LD, R, P, fOUT) Output LOW Voltage (LD, R, P, fOUT) Output HIGH Current (LD, R, P, fOUT) Output LOW Current (LD, R, P, fOUT) Input HIGH Voltage Input LOW Voltage Input Sensitivity fIN OSCin CLK, DATA, LE, FC CLK, DATA, LE, FC 1.0 -10 -5.0 130 -310 1.0 -75 -2.6 +1.4 -15 4.4 2.4 VOL 0.4 0.4 IOH IOL -1.0 1.0 -60 -2.0 +2.0 -1.4 +2.6 +15 nA V V V V mA mA 4. VP = 6.0V, all outputs open. 5. AC coupling, FIN measured with a 1000pF capacitor. 6. Source current flows out of the pin and sink current flows into the pin. 2.0 200 500 0.7VCC 0.3VCC 2.0 1000 2200 MHz MHz mVP-P mVP-P V V A A A A A mA VDo = VP/2; VP = 2.7V VBISW = VP/2; VP = 2.7V 0.5 < VDO < VP - 0.5 0.5 < VBISW < VP - 0.5 VCC = 5.0V VCC = 3.0V VCC = 5.0V VCC = 3.0V VCC = 5.5V VCC = 5.5V VCC = 5.5V OSCin = VCC OSCin = VCC - 2.2V Crystal Mode External Reference Mode Max 10.5 12.5 1.1 1.3 MHz mA Unit mA Note 1 Note 2 Note 3 Note 4 Note 5 Condition Input HIGH Current (DATA and CLK) Input LOW Current (DATA and CLK) Input Current (OSCin) Input HIGH Current (LE and FC) Input LOW Current (LE and FC) Charge Pump Output Current Do and BISW 1. VCC = 3.3V, all outputs open. 2. VCC = 5.5V, all outputs open. 3. VP = 3.3V, all outputs open. VP VCC 10k P 12k 33k EXTERNAL CHARGE PUMP OUTPUT R 12k 10k LD 0.01F 10k LOCK DETECT OUTPUT 100k Figure 8. Typical External Charge Pump Circuit Figure 9. Typical Lock Detect Circuit HIPERCOMM BR1334 -- Rev 4 9 MOTOROLA MC12206 C1 1 OSCin R 16 EXTERNAL CHARGE PUMP (SEE FIGURE 8) LOW PASS FILTER (SEE FIGURE 11) VCO 2 C2 VP 3 100pF VCC 4 100pF 0.1F 5 0.1F OSCout P 15 CHARGE PUMP SELECTION (INTERNAL OR EXTERNAL) VP FOUT 14 VCC BISW 13 MC12206 Do FC 12 6 GND LE 11 LOCK DETECT LOCK DETECT CIRCUIT (SEE FIGURE 9) 7 LD DATA 10 47k FROM CONTROLLER 8 1000pF fin CLK 9 47k C1, C2: Dependent on Crystal Oscillator Figure 10. Typical Applications Example (16-Pin Package) BISW Do OR EXTERNAL CHARGE PUMP R C VCO Figure 11. Typical Loop Filter MOTOROLA 10 HIPERCOMM BR1334 -- Rev 4 MC12206 OUTLINE DIMENSIONS -A - 16 9 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J -B - P 8 PL 0.25 (0.010) M 1 8 B M G F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 K C -T SEATING - PLANE R X 45 M D 16 PL 0.25 (0.010) M J T B S A S DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E-02 ISSUE A 20X K REF M 0.15 (0.006) T U S 0.10 (0.004) TU S V S 2X L/2 20 11 L PIN 1 IDENT 1 10 B -U- J J1 N 0.15 (0.006) T U S A -V- N F C D 0.100 (0.004) -T- SEATING PLANE G H DETAIL E HIPERCOMM BR1334 -- Rev 4 11 IIII IIII IIII SECTION N-N 0.25 (0.010) M DETAIL E K K1 NOTES: 12 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 13 CONTROLLING DIMENSION: MILLIMETER. 14 DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 15 DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 16 DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 17 TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 18 DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 1.20 --- 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 0.047 --- 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ -W- DIM A B C D F G H J J1 K K1 L M MOTOROLA MC12206 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan. ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. MOTOROLA CODELINE TO BE PLACED HERE 12 *MC12206/D* HIPERCOMM MC12206/D BR1334 -- Rev 4 |
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